FIG. 6 is a diagram illustrating a circuit configuration of a conventional compare decision circuit (exclusive OR circuit) (see Patent Document 1 below). This circuit is designed to resolve the problem proper to an exclusive-OR circuit which is consisted by plural stages of gate circuits, such as NOR gates or AND gates, that propagation delay is elongated such that the demand for high operating speed cannot be coped with. This prior-art circuit includes a transfer gate composed by an nMOS transistor NM11 and a pMOS transistor PM11 which are connected in parallel between an input terminal RD and an output terminal CD, and which are supplied at gate terminals thereof with a compare data signal φ 1 and an inverted signal of the compare data signal φ 1, obtained by an inverter INV, respectively for being on-off controlled. The circuit also includes a pMOS transistor PM12 which has a source connected to a power supply VDD and has a gate connected to the input terminal RD, and a pMOS transistor PM13 which has a source, a gate and a drain connected to the drain of the pMOS transistor PM12, to an output of the inverter INV and to the output terminal CD, respectively. The circuit further includes an NMOS transistor NM12 which has a drain connected to the output terminal CD and has a gate connected to the input terminal of the compare data signal φ 1, and an nMOS transistor NM13 which has a source, a drain and a gate connected to the ground, to the source of the nMOS transistor NM12 and to the input terminal RD respectively. The circuit shown in FIG. 6 implements the operating function of the exclusive OR of CD=XOR (φ 1, RD).
That is, when the compare data signal φ 1 is at a low level and the input terminal RD is at a low level, the transistors PM11 and NM11, constituting the transfer gate, are turned on, and the output terminal CD is set to a low level At this time, the transistors PM13, NM12 and NM13 are in an off state.
When the compare data signal φ 1 is at a low level, and the input terminal RD is at a high level, the transistors PM11 and NM11 constituting the transfer gate, are turned on to set the output terminal CD to a high level. At this time, the transistors PM12, PM13 and NM12 are in an off state.
When the compare data signal φ 1 is at a high level, and the input terminal RD is at a low level, the transistors PM11 and NM11, constituting the transfer gate, are in an off state, whilst the transistor PM12 and PM13, connected between the output terminal CD and a power supply VDD, are turned on and the transistor NM13 inserted in the path between the output terminal CD and the ground GND is turned off to set the output terminal CD to a high level.
When the compare data signal φ 1 is at a high level, and the input terminal RD is at a high level, the transistors PM11 and NM11, constituting the transfer gate, are turned off, whilst the transistor PM12 and PM13, connected between the output terminal CD and the power supply VDD, are turned off, and the transistors NM12 and NM13, connected between the output terminal CD and the ground GND, are turned off to set the output terminal CD to a low level.
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-2-3144 (FIG. 1)
[Non-Patent Document]
‘Error Correction Code and its Application’, edited by Picture Information Media Association, supervised by Y. Etoh and T.Kaneko, pages 26 and 34, published by OHM Co. Ltd., on Jul. 20, 2001.